“PrimeTime-SI extends gate level STA signoff to include crosstalk effects on timing and has been integrated into our UNICAD 2.0 design environment.
“PrimeTime-SI seamlessly integrates static timing analysis with crosstalk analysis and delivers the performance and capacity we need to analyze some of our most complex designs, something we couldn’t do with other approaches,” said Jean-Pierre Geronimi, Director of CAD, Central R&D, STMicroelectronics. This makes PrimeTime-SI easy to use and adopt and increases designer productivity. Designers who are familiar with PrimeTime can perform crosstalk analysis throughout the design process without any special expertise or training to do so. In addition, PrimeTime-SI is integrated with the existing design flow and shares the same commands, scripts and libraries with PrimeTime. On customer evaluations, PrimeTime-SI’s timing estimates correlated to within 5-10 percent of SPICE on most nets.
PrimeTime-SI also includes an integrated delay calculation engine that accurately models and computes the signal timing deviation (speed-up or slow-down of nets) due to crosstalk. It is based upon Synopsys’ proven static timing analysis (STA) technology, which provides PrimeTime-SI the capacity to handle multi-million gate designs and the performance to minimize run times. PrimeTime-SI is the industry’s first static timing and crosstalk analysis tool. PrimeTime-SI: Integrated Static Timing and Crosstalk Analysis PrimeTime-SI leverages CAT know-how, ST design experience, and PrimeTime static timing and crosstalk analysis technology, into one product." We have been working closely with Synopsys as a strategic technology partner to develop PrimeTime-SI. ST had developed a crosstalk analysis tool (CAT) that was integrated in a crosstalk aware static timing analysis (CASTA) flow together with PrimeTime. Therefore, the ability to detect and analyze crosstalk quickly is very important to us. As a result, the chip may not meet performance targets.Īccording to Bruno Franzini, Timing Modeling and Signal Integrity Manager, Central R&D, STMicroelectronics, “Crosstalk-induced errors have become a major performance limiting factor on our designs at 0.18 micron and below. Crosstalk, which is caused by capacitive coupling between adjacent wires, can cause a change in the delay of a signal or result in an incorrect logic transition. Crosstalk-induced errors are the most common signal integrity problem. With shrinking process geometries and rising clock frequencies, it is essential for designers to address signal integrity problems to meet timing closure. Called PrimeTime Signal Integrity (PrimeTime-SI), this new product builds upon the market-leading position of PrimeTime, offering static timing and crosstalk analysis in a fully integrated tool. (Nasdaq:SNPS) today announced a new version of its industry-leading PrimeTimeR static timing analysis product to address the growing challenge of detecting and resolving crosstalk on 0.18 micron and below system-on-chip (SoC) designs.
This library is free software you can redistribute it and/or modify it under the same terms as Perl itself, either Perl version 5.8.5 or, at your option, any later version of Perl 5 you may have available.MOUNTAIN VIEW, Calif., Ap- Synopsys, Inc. Three tools provided as gedgets and also examples using PrimeTime::Report.
$pt->clk_path($clock_path, "source") Tools $pt->path_extract($path, $length) clk_path Input1: text which contants clock path information Input1: text which contants path information Split each line by space and create a 2D array. Print the specified path in orignal format. $pt->print_summary("slack", "startpoint", "endpoint") print_path Input1: Path number
$pt->read_file($file) print_summary available input option: startpoint, endpoint, path_group, path_type, clock_domain, clock_period, uncertaintyĬlock_latency_capture, clock_latency_source PrimeTime::Report help you extract useful information from PrimeTime report. PrimeTime::Report - Parser for PrimeTime report.